Semiconductors are treated in most retail analysis as a single sector, and the resulting frame — "buy chip stocks when the cycle turns up" — misses almost everything worth knowing about the industry. The reality is that semiconductors are four distinct layers with different economics, different geographies, different customer bases, and different vulnerabilities. Understanding the anatomy is the entry-level requirement for any serious view.
Layer one: design
At the top of the stack are the designers — Nvidia, AMD, Broadcom, Qualcomm, and Apple (which designs its own silicon). Their business is intellectual property. They own the architectures, the instruction sets, the specialised algorithms. They own nothing physical; they contract out fabrication entirely.
The economics of pure design are extraordinary: gross margins in the 60–80% range, near-zero capital intensity, and a business model that scales with software rather than steel. But the moat is entirely intellectual. When a competitor's design catches up, revenue can compress quickly — the industry's history is a graveyard of once-dominant designers displaced within a decade.
Layer two: manufacturing (foundries)
Below the designers are the foundries — TSMC by an enormous margin, then Samsung, then Intel Foundry Services, then several smaller specialists. Their business is physical production. They operate the fabs, run the process technology, and take in wafer starts from every designer that cannot afford or does not want its own manufacturing capacity.
The economics of foundries are the opposite of designers: gross margins in the 40–50% range, capital intensity that requires tens of billions of dollars per new leading-edge fab, and construction lead times measured in years. The moat is engineering and capital access — a leading-edge fab costs more than most countries' annual defense budgets, and only a handful of companies in the world can build one.
TSMC alone commands over half of the global foundry market and essentially all of leading-edge nodes. This concentration is the single most-discussed geopolitical risk in the industry.
Layer three: equipment
Behind the foundries are the equipment makers — ASML for extreme ultraviolet lithography, Applied Materials for deposition and etch, Lam Research for etch, KLA for inspection, Tokyo Electron for coater/developer. Their business is selling the machines the foundries use.
The equipment layer has moat properties that arguably exceed even the foundries themselves. ASML is the sole global supplier of EUV lithography machines — the technology required for the most advanced logic nodes. There is no second source. This monopoly is the reason ASML's revenue has grown from a specialist niche into a $30-billion global business, and why every export-control conversation about semiconductor technology mentions the company by name.
Layer four: materials and specialty
Below equipment are the specialty layer — wafer producers (Shin-Etsu, SUMCO), photoresist suppliers (JSR, Tokyo Ohka), specialty chemicals, packaging and testing houses. Their business is the consumables and services that keep the fabs running.
The specialty layer is less glamorous but is characterised by very high barriers to switching — a foundry qualifying a new photoresist supplier for a production node can take a year and cost hundreds of millions. This is why the top three suppliers in each specialty niche have often held their positions for decades.
The geographic concentration
Taiwan hosts most of the leading-edge logic capacity (TSMC). South Korea hosts most of the memory capacity (Samsung, SK Hynix). Japan holds the specialty materials layer. The Netherlands holds EUV. The United States holds most of the design layer and much of the equipment layer. Mainland China holds trailing-edge logic capacity and is investing aggressively to move up the stack.
This geographic distribution is why semiconductor policy is now one of the most-watched areas of every major economy's industrial strategy. The concentration is not accidental — it is the result of decades of accumulated engineering capability that cannot be replicated quickly — and the resulting fragility is now a first-order national security concern for every country that depends on advanced chips.
What this means for a reader analysing the sector
Do not read "semiconductor cycle" as a single thing. A memory downcycle can hit Samsung and SK Hynix while ASML's order book grows because a foundry expansion is still in progress. A design cycle in AI accelerators can lift Nvidia while foundry utilisation for consumer chips remains soft. The four layers are correlated but not identical, and reading them separately is the only way to understand which "chip cycle" any given commentary is actually referring to.
The single most useful frame is the customer relationship map. Every layer sells to the layer above it. When you see a headline about any semiconductor company, ask which layer it operates in, which layer above and below it depends on, and which of those relationships is under pressure. Almost every consequential news story in the industry can be located precisely by that framework.
Educational content only. Not investment advice.